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VHDL QUESTIONS

"Readline called past the end of file" error VHDL
"Readline called past the end of file" error VHDL
I hope this helps . As stated in the comment section, you are trying to read more than you have in the file, you can avoid the error by checking if you reached the end of the file in your for loop and in that case assign a default value instead.
TAG : vhdl
Date : January 09 2021, 05:38 AM , By : Bas
in VHDL, is it possible to create an array of std_logic_vector without using a type?
in VHDL, is it possible to create an array of std_logic_vector without using a type?
it fixes the issue What you created is an array of an array - which is in general what you want. What @Matthew Taylor created is a multidimensional array. WIth VHDL-2008 the elements of a composite can be unconstrained, and hence, you can create:
TAG : vhdl
Date : January 02 2021, 06:48 AM , By : David
What's the VHDL equivalent of verilog 2001's “+:” operator?
What's the VHDL equivalent of verilog 2001's “+:” operator?
I think the issue was by ths following , This seems to be a bit of an XY Problem. The Verilog :+ (or -:) operator is a bit of a hack to get round the fact that this kind of thing:
TAG : vhdl
Date : January 02 2021, 06:48 AM , By : jehammon
For Verilog/VHDL simulation: how to open modelsim wlf file from command line?
For Verilog/VHDL simulation: how to open modelsim wlf file from command line?
around this issue With GtkWave I can simply open a vcd waveform file from the command line as follows: , You're looking for the -view option of modelsim:
TAG : vhdl
Date : January 02 2021, 06:48 AM , By : pcoramc
GHDL simulator doesn't support vhdl attributes without error?
GHDL simulator doesn't support vhdl attributes without error?
should help you out See IEEE Std 1076-2008 7.2 Attribute specification, paragraph 9:
TAG : vhdl
Date : January 02 2021, 06:48 AM , By : John Studdert
VHDL: including file type inside of a VHDL Record structure?
VHDL: including file type inside of a VHDL Record structure?
around this issue When I have tried to remove file in your code, I got this error :
TAG : vhdl
Date : January 02 2021, 06:48 AM , By : user105769
in VHDL, how to check if file exists before opening it?
in VHDL, how to check if file exists before opening it?
around this issue In Verilog, I can check if a file exists by opening the file and then checking if the file descriptor is zero, and if it is not to assume the file doesn't exist. For example, as follows: , When you open a file, for example:
TAG : vhdl
Date : January 02 2021, 06:48 AM , By : billputer
need VHDL equivalent of c-language "strtok" and "strcmp" functions that can operator on vhdl string
need VHDL equivalent of c-language "strtok" and "strcmp" functions that can operator on vhdl string
With these it helps I'm trying to write a stimulus reader for vhdl testbench. it needs to read a text command and two text operands delimited by whitespaces in a text file.
TAG : vhdl
Date : January 02 2021, 06:48 AM , By : Gilmar Souza Jr.
VHDL: convert "real" and "time" variables into strings for display on console
VHDL: convert "real" and "time" variables into strings for display on console
Hope that helps This is easy, a type's image attribute is a function that convert that type to a string representation:
TAG : vhdl
Date : January 02 2021, 06:48 AM , By : taviso
VHDL for 2to1 Multiplexer
VHDL for 2to1 Multiplexer
To fix the issue you can do This is what I'm trying to write in VHDL code: , Multiplexer :
TAG : vhdl
Date : January 02 2021, 06:48 AM , By : Mr. Tacos
How do I reduce redundancy in state logic for repeated processes (handshakes)?
How do I reduce redundancy in state logic for repeated processes (handshakes)?
fixed the issue. Will look into that further I ended up using a master-slave FSM as suggested by Matthew Taylor in the comments: How do I reduce redundancy in state logic for repeated processes (handshakes)?. The redundant code was stored in a separa
TAG : vhdl
Date : January 02 2021, 06:36 AM , By : Guy Kastenbaum
If sensitivity list in VHDL is not synthesizable, why does it gives an error due the Analysis and Synthesis?
If sensitivity list in VHDL is not synthesizable, why does it gives an error due the Analysis and Synthesis?
I wish this helpful for you It is the job of a logic synthesiser to generate a circuit that behaves exactly the same as your RTL. A process without a sensitivity list or a wait if an infinite loop and so cannot be simulated. Therefore, given my first
TAG : vhdl
Date : December 28 2020, 01:33 PM , By : pad
How FPGA inferrs the VHDL constatns in the Design after synthesis
How FPGA inferrs the VHDL constatns in the Design after synthesis
wish help you to fix your issue Synthetizer simplifies your design.Synthetizer reduces logic equations to remove constants and use less LUTs.
TAG : vhdl
Date : December 28 2020, 01:33 PM , By : jamerson
How does this SIPO Works?
How does this SIPO Works?
wish help you to fix your issue In VHDL is the concatenation operator. It is used to make bigger arrays from smaller arrays and single array elements by concatenating them, ie joining them together. So,
TAG : vhdl
Date : December 27 2020, 04:45 PM , By : UpperLuck
VHDL: Correctly way to infer a single port ram with synchronous read
VHDL: Correctly way to infer a single port ram with synchronous read
With these it helps Unfortunately, the synthesis tool vendors have made the RAM inference functions so that they typically recognize both styles, regardless of the physical implementation of the RAM in the FPGA in question. So even if you specify reg
TAG : vhdl
Date : December 25 2020, 05:31 PM , By : Ravenal
Blocking Assignments on SIGNALS in VHDL
Blocking Assignments on SIGNALS in VHDL
seems to work fine I will give you an explanation through a digital circuit prism. It is a way of thinking that you have to keep in mind when you develop VHDL.Your valid is at 1 before the clock edge. You are in simulation so you can imagine that all
TAG : vhdl
Date : December 15 2020, 09:15 AM , By : desmiserables
'Opt_Design Error' in Vivado when trying Run Implementation
'Opt_Design Error' in Vivado when trying Run Implementation
seems to work fine You are assigning done both in the first and the second process, which is exactly what the implementation is complaining about, you cannot have multiple drivers. Remove done
TAG : vhdl
Date : December 06 2020, 11:46 PM , By : kbrust
State machine and unsigned signal
State machine and unsigned signal
I hope this helps . I have a few problems with a fairly simple state machine I made. No matter what I do, the signal startS1, startS2, enS and mS always stays unsigned in simulation even when I hit the reset button and I can't figure out why. There's
TAG : vhdl
Date : December 05 2020, 12:18 PM , By : Si Gardner
Delay in Simulation of Output with regard to Input
Delay in Simulation of Output with regard to Input
I hope this helps . Firstly, some comments : Your application (MultiLevel Car Parking) is not very adapted to VHDL language. It's too high level. Your coding style is a bit object oriented (type and variable names). There are syntax errors in your co
TAG : vhdl
Date : December 01 2020, 04:42 PM , By : boney M
How can I get the index of a one-hot encoded vector without using a for-loop?
How can I get the index of a one-hot encoded vector without using a for-loop?
this one helps. There is no "simple" solution for generating the index of a one-hot vector in VHDL.For a one-hot vector of 4 bits, thus a resulting index of 2 bits, the loop you have made is an OK solution, that is readable and does not take up too m
TAG : vhdl
Date : November 24 2020, 12:01 PM , By : sam
What is the recommended way for carrying VHDL code around?
What is the recommended way for carrying VHDL code around?
it helps some times VHDL source code is generally portable between VHDL tool implementations.When a design unit is successfully analyzed it is stored in a library, by default what ever work is, in context.
TAG : vhdl
Date : November 22 2020, 02:59 PM , By : Lior
Why can't make work my VHDL program using elsif not recognize one state
Why can't make work my VHDL program using elsif not recognize one state
wish help you to fix your issue The sen=0010 appears like sen is compared to a 4-bit vector, but it is actually compare with the decimal value 0010 = 10 = ten, due to the lack of "" around the 0010 value. Fix this in all place with by adding "", like
TAG : vhdl
Date : November 22 2020, 10:58 AM , By : Killercode
HDLParsers:800 Type of "**" is incompatible with type of "**"
HDLParsers:800 Type of "**" is incompatible with type of "**"
it helps some times This answer is provided because the other 7 occurrences of ERROR:HDLParsers:800 on Stackoverflow don't involve literals assigned to integer types, and Morten thinks an actual answer to the question may be valuable. The closest mat
TAG : vhdl
Date : November 22 2020, 10:56 AM , By : rajiv
Sensitivity List in VHDL
Sensitivity List in VHDL
this one helps. For a D-latch you want that data_out=data_in as long as enable is '1'. So if data_in changes while enable remains '1', data_out has to change. If data_in where not in the sensitivity list, this would not happen.
TAG : vhdl
Date : November 19 2020, 12:01 PM , By : pdkent
Snake game using FPGA in VHDL
Snake game using FPGA in VHDL
I wish did fix the issue. First of all, I recommend you split your display and your position update functionality into separate processes to make things clearer.You seem to already have mostly everything you need for your display process, except that
TAG : vhdl
Date : November 18 2020, 11:13 AM , By : user177837
VHDL: Help understanding time steps/states and concurrency
VHDL: Help understanding time steps/states and concurrency
To fix this issue Concurrency of the comparatorImagine that right after the clock edge, the state signal has been updated. You've got one clock period to do a comparison and set the next state.
TAG : vhdl
Date : November 16 2020, 11:00 PM , By : baumichel
Non resolved signal has multiple sources VHDL
Non resolved signal has multiple sources VHDL
To fix this issue Your error message: non resolved signal NS has multiple sources contains also the source lines, which causes the multiple driver issue. See the full Xilinx XST synthesis report.More over, your code has multiple copy-paste errors:
TAG : vhdl
Date : November 16 2020, 06:23 AM , By : AJacques
FSM in VHDL is Moore or Mealy?
FSM in VHDL is Moore or Mealy?
This might help you It is a Moore state machine, since the outputs unlock and warning depend only on current_state in the combinatorial_logic_p process.Note that the signals errors_num and five_cycles are used in the combinatorial_logic_p process, bu
TAG : vhdl
Date : November 13 2020, 04:01 AM , By : Brian
operation of std_logic:='X'
operation of std_logic:='X'
wish helps you The type std_logic is an enumeration type with 9 values and has the following 9 values:
TAG : vhdl
Date : October 09 2020, 03:00 AM , By : Hugo
In VHDL-2008, how to format "real" similar to "%f" in c-language, example: sprintf(str, "%9.6f&
In VHDL-2008, how to format "real" similar to "%f" in c-language, example: sprintf(str, "%9.6f&
To fix the issue you can do I'm using VHDL-2008 and I want to nicely format real numbers are strings similar to this c-language function: , VHDL 2008 provides to_string for real in 3 flavours:
TAG : vhdl
Date : October 07 2020, 09:00 PM , By : baumichel
Latch data when differs from zeros
Latch data when differs from zeros
wish helps you This looks like a delta race condition where NotZero and Data are both dependent on inData, but Data is also dependent on NotZero = '1'. NotZero changes to '0' in the current delta cycle, but the Data expression has not seen this updat
TAG : vhdl
Date : October 07 2020, 08:00 AM , By : user130518
How to emulating C++ classes in VHDL-2008 or above
How to emulating C++ classes in VHDL-2008 or above
may help you . Is there a way to emulate the data encapsulation features of a C++ class in VHDL-2008 using just VHDL functions and VHDL records? I've seen this type of thing done many times in languages such as "c", but very rarely for VHDL. , What I
TAG : vhdl
Date : October 07 2020, 08:00 AM , By : Pepe Araya
VHDL: bound check error when adding two numbers
VHDL: bound check error when adding two numbers
it should still fix some issue The vector operand of the addition should have the same length as the target of the assignment. Extend if needed:
TAG : vhdl
Date : October 06 2020, 03:00 PM , By : Nandor Devai
VHDL: setting a constant conditionally based on another constant's value
VHDL: setting a constant conditionally based on another constant's value
hope this fix your issue I need to set a constant's value using an "if-else" or "case", and select a different constant value based on another constant's value. Is this possible in VHDL? It would be a one time change of constant values at the beginni
TAG : vhdl
Date : October 06 2020, 07:00 AM , By : Matt Logan
image rom display VGA
image rom display VGA
hop of those help? i am doing code using VHDL FPGA the code content 3 part first one VGA and second one is rom code and third draw image one is save of image rom display vga and get he problem , IEEE Std 1076-200812.4 Use clauses
TAG : vhdl
Date : October 05 2020, 01:00 AM , By : n1ckless_id
What's the equivalent of Verilog tilde operator "~" in VHDL?
What's the equivalent of Verilog tilde operator "~" in VHDL?
it helps some times In Verilog and c-language, I can easy negate a vector by using the tilde operator. Example: , The not operator:
TAG : vhdl
Date : October 04 2020, 08:00 PM , By : Comfly
Is "xor" bitwise or logical in VHDL?
Is "xor" bitwise or logical in VHDL?
this will help "logical" operators in Verilog (and C) are just an abbreviation resulting from the (mathematically incorrect) definition that anything nonzero is assumed "true" while a zero value is assumed "false". Such
TAG : vhdl
Date : October 04 2020, 08:00 PM , By : Monev
VHDL parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK Process "Check Syntax"
VHDL parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK Process "Check Syntax"
I wish this help you In VHDL when you want to access to a particular element of an array (std_logic_vector are array), you have to use () instead of [].
TAG : vhdl
Date : October 03 2020, 02:00 AM , By : Erik
How can we assign different signals to a single integer value?
How can we assign different signals to a single integer value?
should help you out I'm writing VHDL test bench for full adder , Yes you can - VHDL 2008 allows aggregate assignments.
TAG : vhdl
Date : October 02 2020, 05:00 PM , By : Robin Buitenhuis
How to find amplitude and frequency of an incoming sinusoidal signal (analog) in VHDL
How to find amplitude and frequency of an incoming sinusoidal signal (analog) in VHDL
seems to work fine The VHDL MAXIMUM function returns the maximum (ie larger) value of its two inputs. Your two inputs are input_sine and S_amp, which is always 0.0. So, Amp_out will equal input_sine when input_sine is positive and 0.0 when it is nega
TAG : vhdl
Date : September 28 2020, 07:00 PM , By : ChaseVoid
How can i use floating point numbers in VHDL?
How can i use floating point numbers in VHDL?
hop of those help? you can this using integer multiplication.If you have a FPGA with 18 bit multipliers you multiply and then use the upper bits.
TAG : vhdl
Date : September 28 2020, 03:00 PM , By : user181945
maximum number of ports in a Verilog module or a VHDL entity
maximum number of ports in a Verilog module or a VHDL entity
wish help you to fix your issue The SystemVerilog LRM says, in 23.2.2 Port declarations
TAG : vhdl
Date : August 24 2020, 03:00 AM , By : Grace Jones
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